1. Field of the Invention
The invention relates to a data processing apparatus comprising:
a data processing element, having an operating mode and a stop mode, said element comprising a data input a first data output, a reset signal input, a clock input a stop signal output and first power supply terminal means; PA0 oscillator means for feeding said clock input with clock pulses, said oscillator means having second power supply terminal means; PA0 a data receiving module for receiving external data, said module having a second data output connected to the data input; PA0 switching means, interconnected between said second power supply terminal means and said oscillator means, the switching means having a first control input for detecting an interrupt signal produced by said data receiving module for thereupon driving said switching means to an operating power transmitting state for said second supply terminal means and a second control input fed by said stop signal output for upong detection of a stop signal generated by said data processing element driving said switching means to a stand-by power transmitting state for said second supply terminal means; PA0 a transition signal detector connected between said switching means and said reset signal input for upon detecting any transition from said stand-by power transmitting state to said operating power transmitting state generating a reset pulse, that has a trailing edge occurring only after termination of said predetermined time interval.
wherein said data processing element has reset means for under combined control of a series of clock pulses and a reset signal on said reset input attaining an initial state within a predetermined line interval, the data processing apparatus being suited for economically consuming energy.
2. Prior Art
Reducing energy consumption is of interest in environments of limited available power, e.g. in implanted medical devices, portable equipment or space satellites and in devices in which energy dissipation should be limited, e.g. in VLSI circuits.
A first method for reducing energy consumption in a clocked data processing apparatus, designed in a low-power technology, would be to lower the frequency of the clock as far as possible regarding the required data throughput. Problems then occur, in that DC-current paths, which can be hidden in the design of the data processing element, will be open for a longer period, thereby partially undoing this reduction, and also in that real-time processing may be no longer possible.
A second method for reducing energy consumption would be to use a data processing element, having an operating mode and a mode of reduced activity, and to switch between these modes, keeping the element in the latter mode as long as no operating is required, in which mode the consuming of energy is less than in the former mode. A data processing element having an operating mode and modes of reduced activity is for example the single-chip 8-bit microcontroller PCB80C31, (Philips Data Handbook IC14N, 1985, pp. 187-213). This element has a mode of reduced activity called the idle mode, in which mode the CPU is frozen, while the RAM, timers, etcetera continue functioning, and a mode of further reduced activity, called the stop mode, in which mode the RAM contents are saved but the oscillator is frozen causing all & other chip functions to be inoperative. The energy consumed in the stop mode per unit time can be ignored with respect to the energy consumed in the idle mode. The idle mode as well as the stop mode are activated by software.